Implementing Atomic Operations

Qt uses an optimization called implicit sharing for many of its value classes.

Starting with Qt 4, all of Qt's implicitly shared classes can safely be copied across threads like any other value classes, i.e., they are fully reentrant. This is accomplished by implementing reference counting operations using atomic hardware instructions on all the different platforms supported by Qt.

To support a new architecture, it is important to ensure that these platform-specific atomic operations are implemented in a corresponding header file (qatomic_ARCH.h), and that this file is located in Qt's src/corelib/arch directory. For example, the Intel 80386 implementation is located in src/corelib/arch/qatomic_i386.h.

Currently, Qt assumes that the following operations have been implemented:

• int q_atomic_test_and_set_int()
• int q_atomic_test_and_set_acquire_int()
• int q_atomic_test_and_set_release_int()
• int q_atomic_test_and_set_ptr()
• int q_atomic_increment()
• int q_atomic_decrement()
• int q_atomic_set_int()
• int q_atomic_set_ptr()

Note that these functions must be atomic with respect to both interrupts and multiple processors.

Warning: The functions mentioned in this document are used internally by Qt and are not part of the public API. They may change in future versions of Qt. The purpose of this document is to aid people interested in porting Qt to a new architecture.

 if (*ptr == expected) {
     *ptr = newval;
     return !0;
 }
 return 0;

 if (*ptr == expected) {
     *ptr = newval;
     return !0;
 }
 return 0;

 ++(*ptr);
 return *ptr ? !0 : 0;

 return ++(*ptr);

 ++(*ptr);
 return !(ControlRegister & ZeroFlag);

 --(*ptr);
 return *ptr ?  : 0;

 return --(*ptr);

 --(*ptr);
 return !(ControlRegister & ZeroFlag);

 tmp = *ptr;
 *ptr = newval;
 return tmp;

 tmp = *ptr;
 *ptr = newval;
 return tmp;